The present invention relates to high speed serial communications/data transfers between integrated circuits or systems and more particularly to a method and circuit for implementing the best data sample selection in a data recovery circuit based on an oversampling technique when the incoming data stream suffers from jitter and is skewed with respect to the reference clock.
In the field of high speed serial communications/data transfers between integrated circuits or systems, data recovery circuits are extensively used. Let us assume the presence of a separate oversampling circuit generating a plurality of data samples during each bit period. We also assume the presence of an edge detector circuit able to detect the occurrence of a data transition between two consecutive data samples. The best sample to represent the recovered data is the sample which is the farthest from the data edges (or data transitions).
FIG. 1 shows a typical eye diagram for a high speed serial data link. Data jitter or phase error (skew) between clock and data thus significantly reduce the useful sampling window. One can notice that the reliable sampling window (hatched area) corresponding to the zone where the data bit is guaranteed to be stable can be significantly shorter than the bit period T. Furthermore, circuit process deviations, operating temperature and power supply variations can also have a negative impact on sampling window width and thus on the targeted circuit accuracy.
The selection of the best sample generally relies on a training pattern specific to the data communication protocol in consideration. The training pattern is used during a calibration step to determine which clock phase is the best to recover the data and this calibration step is repeated whenever required. As a consequence, a data recovery circuit built for a given communication data protocol is generally not suitable to recover data sent using a different data communication protocol since it will be unable to recognize the training pattern and thus to select the best data sample.
On the other hand, the duration of the training patterns is relatively short compared to the data duration and therefore are not representative of the jitter affecting the data. Moreover, when there is a low number of physical links, it is possible to use phase locked loop oscillators (PLLs) to individually recover the data stream by locking the PLL frequency on the data stream frequency and by generating a sampling clock positioned right in the middle of the data bit. However as soon as there is a large number of data links to handle, it becomes impossible to implement as many PLLs as data links. Finally, the different data link signals may be skewed together by a relatively large amount of time for layout or fabrication process reasons so that it is not possible to reliably sample each data link using a same clock phase.
Consequently, there is a need for an improved data recovery circuit that would be independent of any data communication protocol and capable to support jitter undesirable effects and skew, i.e., the phase difference between any data link signal and an arbitrary synchronous reference clock.